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sva
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SimVision Assertions
I have an assertion along the lines of : assert property( @(posedge clk) A |-> B ); When I run this on Cadence, I get that the assertion failed. Looking at the waveform (counter example), it shows that when A occurs on the negedge of the clock, Cadence is still checking to see if B happened. And when...
Posted to
Functional Verification
(Forum)
by
pdar
on Fri, Jul 29 2011
M/S Technology on Tour Blog – Model Validation and Assertion Based Verification
In February 2011, I had the opportunity to meet a group of analog and mixed-signal design and verification engineers in Boston, Austin and Irvine as part of the Cadence Mixed-Signal Tech-on-Tour program . This was a revealing experience for me in many ways. Having been intimately involved with the AMS...
Posted to
Mixed-Signal Design
(Weblog)
by
PrabalB
on Tue, Jun 28 2011
DAC Preview: The Complete Incisive Enterprise Verifier Submission to John Cooley’s “Cheesy Must See List”
Understandably, EDA industry observer John Cooley had to edit down all the submissions to his annual DAC "Cheesy Must See List" . Hence, allow us to share the complete text that we submitted for Incisive Enterprise Verifier's Assertion-Driven Simulation capability . Hope to see you in San...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Fri, Jun 3 2011
DAC Preview: Make Assertions Come Alive with Assertion-Driven Simulation
While Assertion-Based Verification (ABV) has been around for many years, ABV has largely been a passive exercise. For example, assertions can monitor behavior in a simulation environment, model a formal analysis environment with constraints, or provide targets for formal proofs as checks or covers. This...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, May 31 2011
Free Webinar This Thursday: Rapid Design Bring-Up Using Formal and Simulation Together
Allow us to shamelessly promote a free webinar (including a live demo) this Thursday May 12 at 10am-11am Pacific time, entitled "Verification 1-2-3 with Assertion-Driven Simulation" . In a nutshell, in this webinar Solutions Architect Chris Komar and Product Management Director Joe Hupcey III...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, May 9 2011
DVClub: Verification Users Discuss Assertion Challenges and Solutions
Assertion-based verification has many advantages, but is not particularly easy to use. At Silicon Valley DVClub April 26, two engineers discussed the benefits and challenges of assertions, and described their experience with two tools that help answer the question, "who's going to write all...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 26 2011
Video Easter Egg: Incisive Formal Verifier and SVA driving a Rubik's Cube robot
Just in time for Easter, Team Verify's Apurva Kalia, Manu Chopra, and Suman Ray of the Incisive R&D team created a Rubik's Cube solving Lego robot. However, unlike other such 'bots (recall the now famous ARM-driven Rubik's Cube ‘bot at ARM's TechCon ), the brain of this...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Apr 21 2011
Will Evolving Language Standards Address Mixed-Signal Verification Problems?
Mixed-signal verification has been one of the hottest topics in the past year, and it was very evident in DVCon 2011, looking at the number of technical papers submitted on this topic. Engineers are looking for solutions to solve tough problems in this space, and the creativity put into developing custom...
Posted to
Custom IC Design
(Weblog)
by
Raggie
on Mon, Apr 18 2011
Video: DVCon 2011 Update From NextOp CEO Yunshan Zhu
At DVCon 2011 I had the opportunity to catch-up with NextOp's CEO Yunshan Zhu, where in this video he shares some anecdotes about the BugScope's performance in real world customer environments (including accelerating assertions in Palladium with -0- (zero, zip, zilch, nada) hardware overhead...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Mon, Mar 21 2011
DVCon Paper: Assertion-Based Verification For Mixed-Signal Designs
Digital designers and verification engineers are reaping great benefits from assertion-based verification. Why should analog/mixed-signal designers be left out? A Cadence paper presented at the recent DVCon conference showed how assertions can be applied to the analog/mixed-signal world as well. The...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 10 2011
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