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# stimulus

• #### Multiply number, USING ISTIM

(a) Hey I have a function in a netlist where I want to multiply two numbers as follows: .FUNC u() = a*b But here I will not get the multiplication as asterisk will cause the rest of the line to be taken as a comment. What can I do? (b) For the command I top bot STIMULUS = (V(top)-V(bot))/Resistance(...
Posted to Functional Verification (Forum) by Dan Hansen on Fri, Oct 25 2013
• #### The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos. Interface UVC Environment Virtual Sequencer - Sequence Module UVC Scoreboard DUT Functional Coverage Testbench Test Configuration Factory Phases...
Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Sep 4 2012
• #### Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...
Posted to Functional Verification (Weblog) by Axel Scherer on Wed, Aug 1 2012
• #### Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos . The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into...
Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 23 2012
• #### UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action . It is a must see for the cowbell aficionado. Coincidentally...
Posted to Functional Verification (Weblog) by Axel Scherer on Mon, Jul 16 2012
• #### My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647) Initially I thought: "What is the fuss all about?" While exploring the language during the development of the cowbell videos , it hit me -- I started to recognize the power of Aspect Oriented...
Posted to Functional Verification (Weblog) by Axel Scherer on Tue, Jul 10 2012
• #### Inefficiency is Futile – Gain UVM e and SystemVerilog Verification Productivity Using Save, Restore, and Reseed

In the world of Star Trek " resistance is futile " when you encounter the Borg . Fortunately, in verification we do not have to deal with the Borg. Nonetheless, our world provides plenty of challenges. Schedules are tight, problems are complex, and market windows are narrow. In other words...
Posted to Functional Verification (Weblog) by Axel Scherer on Fri, Jun 1 2012
• #### UVM e (IEEE 1647) Video Series Features the Return of the Cowbell!

A significant number of readers of my previous post on this topic were not aware of the Saturday Night Live cowbell skit. This took me quite by surprise! The only prescription for this problem is that I pledge to continue to play the cultural ambassador and will introduce more vital trivia! However,...
Posted to Functional Verification (Weblog) by Axel Scherer on Mon, May 21 2012
• #### UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

To quote an American pop culture catchphrase made famous by Saturday Night Live character Bruce Dickison , "I gotta have more cowbell !" In the world of functional verification this translates to "more collateral!" Thererfore, we have released a set of byte-size videos about the basics...
Posted to Functional Verification (Weblog) by Axel Scherer on Thu, May 3 2012
• #### Help with capture CIS Vstim stimulus editor

I have built an amplifier circuit on orcad CIS and i want to give it a Vstim AC input so that I can see the output. I chose Vstim/sourcstm, right clicked on it and choose edit pspice stimulus, choose a SIN stimulus, choose amplitude, frequency and offset value, and press apply, then ok. I then press...
Posted to Feedback, Suggestions, and Questions (Forum) by icecoldness on Wed, Apr 14 2010
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