Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> static timing analysis
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
Verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
static timing analysis
"SoC-Encounter"
.lib
8.1
advanced node
AMS
AMS Verification
analog
analog behavioral models
analog behavoral
analog/mixed-signal
app note
ARM
ARM Cortex M0
ARM-Cortex-M
cadence
Cadence Encounter Power System
CDNLive
CeltIC NDC
Constraint design & validation
corner analysis
cortex M
Cortex-M0
crosstalk
CTE-TCL
Debug
debugging
design closure
design for test
design rules
DFM
DFT
Digital end-to-end flow
Digital Implementation
Digital Implementation forums
digital on top
DRC
Dua
dynamic rail analysis
Early Rail Analysis
ECO
EDI
EDI system
EM Failures
Encounter
Encounter Digital Implementation
Encounter Timing System
EPS
Equivalence checking
ETS
ETS create_spice_deck
Extraction
Fast SPICE
First Encounter
floorplanning
Floorplanning and Prototyping
Formal analysis
friday fun
FTM
full timing model
full-chip integration
Functional Verification
gate level
gate-level debug
gate-level debugging
gate-level simulation
gate-level simulation survey
Global Timing Debug
Incisive
Industry Insights
liberty model
Logic Design
microcontrollers
mixed signal
mixed signal design
mixed signal implementation
Mixed signal physical implementation
mixed signal solution
Mixed-Signal
noise analysis
oa
open access
OpenAccess
power analysis
scripting
SI analysis
signal integrity
signoff
Signoff Analysis
simulation
Spectre
SPICE
SSTA
STA
static analysis
tapeout
TCL
Timing analysis
timing convergence
timing model
Virtuoso
Whitepaper Review: Improving Gate-Level Simulation Performance
As I wrote in a January 2013 blog post , a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation time and over half the debugging time. Since gate-level simulation is much slower than RTL simulation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 18 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
User Video and Presentation: Mixed-Signal Design Using OpenAccess
A distinctive aspect of the Cadence Mixed-Signal Solution is the use of the OpenAccess database to integrate custom/analog (Virtuoso) with digital (Encounter Digital Implementation System) design. Embedded memory provider Spansion has given this methodology a thorough road test, as reported at the 2012...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 14 2013
Mixed Signal Technology Summit Proceedings Now Available
In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
Posted to
Mixed-Signal Design
(Weblog)
by
nizic
on Thu, Dec 13 2012
SPICE Correlation Made Easy by Encounter Timing System (ETS)
Hello, and welcome to my first blog! As an application engineer in customer support, I have received quite a few queries on how to do SPICE correlation of timing numbers. This blog is intended to help users understand the flow/methodology for doing SPICE correlation of static timing analysis (STA) timing...
Posted to
Digital Implementation
(Weblog)
by
MJ Cad
on Mon, Dec 10 2012
Why Multi-Mode, Multi-Corner (MMMC) ECO Closure Requires a New Signoff Approach
In the semiconductor design flow, engineering change orders (ECOs) are as inevitable as death and taxes. While this has always been the case, ECO timing closure is becoming increasingly difficult as the number of operating modes and process-voltage- temperature (PVT) corners skyrockets. What's needed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 6 2012
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react...
Posted to
Mixed-Signal Design
(Weblog)
by
paragb
on Wed, May 16 2012
Bringing Static Analysis Methods to Mixed Signal Designs
Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs. The functional verification of mixed -signal designs has never been completely possible. It is very common to use behavioral models of analog/mixed-signal blocks during the full chip...
Posted to
Mixed-Signal Design
(Weblog)
by
RajendraPratap
on Fri, Aug 26 2011
Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
Posted to
Digital Implementation
(Weblog)
by
PeteMc
on Wed, Feb 23 2011
Programmatically Capturing Cell Delay In The Encounter Digital Implementation System
A while back we were talking about how to programatically troubleshoot timing violations in Encounter . That post recieved a lot of good comments (thanks!) but one in particular touched on a point that I've worked on with other users, so I thought to raise it up for visibility here and go more in...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Fri, Jul 23 2010
Page 1 of 2 (18 items) 1
2
Next >