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A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react...
Posted to
Mixed-Signal Design
(Weblog)
by
paragb
on Wed, May 16 2012
Bringing Static Analysis Methods to Mixed Signal Designs
Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs. The functional verification of mixed -signal designs has never been completely possible. It is very common to use behavioral models of analog/mixed-signal blocks during the full chip...
Posted to
Mixed-Signal Design
(Weblog)
by
RajendraPratap
on Fri, Aug 26 2011
Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
Posted to
Digital Implementation
(Weblog)
by
PeteMc
on Wed, Feb 23 2011
Programatically Capturing Cell Delay In The Encounter Digital Implementation System
A while back we were talking about how to programatically troubleshoot timing violations in Encounter . That post recieved a lot of good comments (thanks!) but one in particular touched on a point that I've worked on with other users, so I thought to raise it up for visibility here and go more in...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Fri, Jul 23 2010
Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient
Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule. A major stumbling block that can be a real threat to that predictability is iterations between different...
Posted to
Digital Implementation
(Weblog)
by
mikeNaustin
on Wed, Mar 10 2010
Design Signoff Begins In Implementation
As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...
Posted to
Digital Implementation
(Weblog)
by
PeteMc
on Wed, Jan 6 2010
Friday Fun: Cutting Ties to the Past
In last week's installment , we left the Dante Semiconductor team when they were nearing tapeout, but their old vendor was asserting its own interests over that of the project. In this week's episode, the team comes together to break the final link so that they can move forward with taping out...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Fri, Aug 28 2009
Does Noise Analysis Accuracy Really Matter?
There have been a lot of new faces springing up in the signoff analysis market over the past few years and the trend seems to be pointing toward products that deliver quick and reasonably good timing signoff with some signal integrity analysis tacked on as an afterthought. This prompted me to ask the...
Posted to
Digital Implementation
(Weblog)
by
mikeNaustin
on Tue, Mar 17 2009
Programmatically Troubleshooting Timing Violations With "report_timing -collection"
Has something like the following ever happened to you? You've placed and optimized a design, and you see what appears to be timing violations that could be fixed with cell changes on the worst path in the design. Like the path below that has a lot of "X1" strength cells (don't worry...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Mon, Feb 9 2009
Innovate Your Way Out of Recession With the New Encounter!
It's official! The U.S. economy has been in a recession for the past year. And, the global credit crunch and economic recession has pulled the semiconductor industry down to the point of entering its eleventh recession. "I'm sorry it's happening," said US President George W. Bush...
Posted to
Digital Implementation
(Weblog)
by
RahulD
on Wed, Dec 3 2008
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