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stacked die,TSV,Industry Insights

Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs

T he recent TSMC Open Innovation Platform (OIP) 2012 Ecosystem Forum marked the release of 20nm and chip-on-wafer-on-substrate (CoWoS) reference flows, as well as new insights about the giant foundry's plan for 16nm FinFETs. I blogged about the keynote speeches here . Separately, I interviewed one...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 24 2012
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 14 2012
Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption

The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries, outsourced assembly and test (OSAT) providers...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 21 2012
EDA Symposium: Users Cite 3D-IC Design Tool Needs

What's needed to bring 3D-ICs with through-silicon vias (TSVs) - or 2.5D ICs with silicon interposers - into the IC design mainstream and volume production? That question resonated through a day-long session on 3D-ICs at the Electronic Design Processes Symposium ( EDPS ) April 6, 2012 in Monterey...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 9 2012
An Update on the JEDEC Wide I/O Standard for 3D-ICs

One of the big advantages of 3D-ICs with through-silicon vias (TSVs) is the potential for much faster memory bandwidth compared to conventional 2D ICs. That's why the emerging JEDEC wide I/O mobile DRAM memory standard, which takes full advantage of 3D die stacking to provide significant power and...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 15 2011
Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011

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stacked die,TSV,Industry Insights

Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs

DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption

EDA Symposium: Users Cite 3D-IC Design Tool Needs

An Update on the JEDEC Wide I/O Standard for 3D-ICs

Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs