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stacked die

  • An Update on the JEDEC Wide I/O Standard for 3D-ICs

    One of the big advantages of 3D-ICs with through-silicon vias (TSVs) is the potential for much faster memory bandwidth compared to conventional 2D ICs. That's why the emerging JEDEC wide I/O mobile DRAM memory standard, which takes full advantage of 3D die stacking to provide significant power and...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 15 2011
  • Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

    A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011
  • DAC 2010 – A “Coming Out” Party For 3D-IC Design

    Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking. The recent M&A activity also brought in some rays of sunshine. The EDA360 vision for the entire industry resonated with a wide gamut of system...
    Posted to Digital Implementation (Weblog) by RahulD on Mon, Jun 28 2010
  • 3D IC Standards – First, Let’s Define Our Terms

    There's a lot of interest in 3D ICs these days, but there are many challenges to solve before 3D IC design can move into the mainstream. One challenge is the establishment of standards for design, modeling, and manufacturability. But the starting point is likely to be something even simpler - a dictionary...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 10 2010
  • Physicist: Quantum Uncertainty May Stall Moore’s Law

    The Embedded Systems Conference could hardly have found a more interesting keynote speaker than Dr. Michio Kaku , a well-known author and theoretical physicist who recently wrote a book entitled " Physics of the Impossible ." As a frequent watcher of his programs on the Science Channel , I...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 29 2010
  • EDA Workshop: A Reality Check On 3D ICs

    3D ICs are an attractive technology, but what will it take to make them successful? Presenters at the recent Electronic Design Processes (EDP) workshop didn't have all the answers, but they had a lot of interesting insights into how EDA tools and flows will need to change to support stacked die with...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 19 2010
  • EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

    Every April the leading edge of the leading edge of semiconductor industry meet at the Electronic Design Process (EDP) Symposium to address design problems that make design more difficult than it should be. This was my first visit and chance to rub shoulders with the industry's gurus and to discuss...
    Posted to Digital Implementation (Weblog) by RahulD on Fri, Apr 16 2010
  • My DATE With 3DIC Technology

    This year DATE (Design, Automation and Test in Europe) was in snowy cold Dresden, Germany, March 8th-March 12 th and offered several 3DIC topics during the conference. I heard someone say "How did 3D with TSVs become hot from cold just so quickly?" In fact it did. Last year when I was following...
    Posted to Digital Implementation (Weblog) by samtabansal on Mon, Mar 29 2010
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