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spice,ARM
106.1.0
14nm
14SOI
16nm
3D
3D transistor
Altos
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BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor
A 3D multi-gate transistor called the FinFET promises tremendous power and performance advantages at 16nm and 14nm process nodes (and was adopted at 22nm by Intel) -- but nobody can use FinFETs without an accurate compact model. Fortunately, the BSIM-CMG model available from the University of California...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 21 2013
Mixed Signal Technology Summit Proceedings Now Available
In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
Posted to
Mixed-Signal Design
(Weblog)
by
nizic
on Thu, Dec 13 2012
ARM TechCon: Inside Story of a 14nm FinFET Tapeout
The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 31 2012
Page 1 of 1 (3 items)