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spectre,veriloga

  • Is there a way in Verilog-A to know if transient noise analysis is run?

    Hi. I'm running IC6.1.5.500.12 with MMSIM 12.1.0.435.isr7. I know the 'if (analysis("tran"))' Verilog-A statement can be used to select code to run when transient analysis is run, but how do I tell in Verilog-A if transient noise analysis is run? Is there some other option for the...
    Posted to Custom IC Design (Forum) by SharksFan on Thu, Sep 19 2013
  • Noise sources in PSS analysis

    Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...
    Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
  • Re: Problem in Cadence Virtuoso AC analysis

    Hi Andrew, I had a little doubt on what parameters are explicitly needed for ac analysis. This is because I am using verilog -A based models and hence want to be sure if I am doing the right thing. As far as I know, AC analysis first computes the DC operating point: so I must define current at each operating...
    Posted to Custom IC Design (Forum) by OneNewBoy on Mon, Mar 25 2013
  • Re: Specify a file path as a parameter type in Cadence VerilogAMS

    I am using the spectre simulator and it is a veriloga view that I am trying to simulate. Thanks, Uzzy
    Posted to Custom IC Design (Forum) by uzzy on Wed, Oct 3 2012
  • BSIM4 cadence implementation

    Hi everyone. Is BSIM4 model implemented in cadence is anyhow different from the official one specified by BSIM group? This derives from comparing a verilog-a model released from another company also implementing BSIM4 also against the cadence one and the results are somehow different. For example parameters...
    Posted to Custom IC Design (Forum) by soathana on Wed, Jul 4 2012
  • verilog-a - model ac biasing

    Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre. kind regards, Sotiris
    Posted to Custom IC Design (Forum) by soathana on Thu, May 10 2012
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