Home > Community > Tags > spectre netlist/Virtuoso
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

spectre netlist,Virtuoso

  • Noise sources in PSS analysis

    Hi all, I have a pretty simple doubt. I am using Verilog A based circuit netlist to perform circuit simulation in cadence spectre. I have defined some flicker noise sources in the same netlist. If I simulated a simple differential amplifier, I can get the inut referred noise through noise analysis. Now...
    Posted to Custom IC Design (Forum) by OneNewBoy on Tue, May 14 2013
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • adding white and flicker noise sources in cadence virtuoso

    Hi all, I am new to cadence virtuoso/spectre. I want to design an ADC for which I have written some components through verilog A containing their respective noise models implemented through white_noise and flicker_noise functions. Now how to activate those sources in spectre simulation ? It's only...
    Posted to Custom IC Design (Forum) by OneNewBoy on Thu, Feb 14 2013
  • Calculation of Sub Threshold and Gate Leakage Power

    Dear Sir, I am working on 6t SRAM cell and want to calculate Sub Threshold and Gate Leakage power of that. So please help me and tell me the steps to calculate the sub threshold and gate leakage power.
    Posted to Custom IC Design (Forum) by Shyam Akashe on Mon, May 30 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Have device connectivity added as an include?

    Hi, Presently, the device connectivity portion of the input file is added as a "cat" function where every single line of the device connectivity shows up as a line in the input file. Is there any hidden switch to change the behavior so that the device connectivity shows up as a single .include...
    Posted to Custom IC Design (Forum) by SharksFan on Fri, Aug 13 2010
Page 1 of 1 (6 items)