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specman

Re: time between two events

Between two different events, or two occurences of the same event? Here's an example for the latter case, I'm sure you can figure out how to modify it for the former. extend sys { !last_time : time; event reset; on reset { var delta := last_time - sys.time; print delta; last_time = sys.time;...

Posted to Functional Verification (Forum) by StephenH on Thu, Oct 11 2012
Re: time between two events

you have sys.time and sys.realtime. You can log the time value when an event happens (using for example and on block) and next time you can calculate the delta. -hannes

Posted to Functional Verification (Forum) by hannes on Thu, Oct 11 2012
Using pli_access for Stubless Indexed Ports

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array elements with the port indexes. Ports in general, and Indexed ports specifically, are static objects...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Oct 9 2012
Re: Specman Tutorial

Hi Pravin. Welcome to the Specman world! I'm sure you will like it here ;-) If you crank up the "cdnshelp" tool and look under the "Incisive Verification Kits" topic you will find a wealth of self-paced tutorials / workshops to experiment with. These guide you through constructing...

Posted to Functional Verification (Forum) by StephenH on Mon, Sep 17 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models

As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 17 2012
UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation. Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
What Does it Take to Migrate from e to UVMe?

So you are developing your verification environment in e , and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
Designer View – Using Metric-Driven Verification for Mixed-Signal IP

Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 29 2012
A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help? Knowing that this customer compiles their e code, and...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Aug 15 2012
Re: RE: Verification Plan using Eplanner

Hello Mahi. Please note that set_cover_check() has nothing to do with disabling checks, it only controls the coverage of the checks. Assuming that you want to disable the coverage of the checks but keep the checks active for error checking, then set_cover_check() is the right method to use. However I'm...

Posted to Functional Verification (Forum) by StephenH on Tue, Aug 14 2012

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specman

Re: time between two events

Re: time between two events

Using pli_access for Stubless Indexed Ports

Re: Specman Tutorial

Webinar: New Interface Links Specman e Language to SystemC TLM Models

UVM Testflow Phases, Reset and Sequences

What Does it Take to Migrate from e to UVMe?

Designer View – Using Metric-Driven Verification for Mixed-Signal IP

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Re: RE: Verification Plan using Eplanner