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software

System-Level Low Power Design – What Will it Take to Move There?

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
Is System Modeling the Next EDA Abstraction Level?

According to a recent talk by Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, the answer is "yes." System modeling is a level of abstraction that's independent from hardware and software implementation. But there are some interesting...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 15 2012
Trying to Make Sense of the Chaos – Impressions from Design West 2012

Walking the show floor of "Design West," the show formerly known as "Embedded Systems Conference," I was as confused as ever. This was the most diverse exhibition I have ever been to. The 222 exhibitors varied from vendors offering system-level modeling with UML/SysML, lifecycle tracking...

Posted to System Design and Verification (Weblog) by fschirrmeister on Tue, Apr 3 2012
EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More

What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 5 2012
Differentiation Through Hardware is Not Going Away

Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that hardware design is not going away, but that the costs...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Mar 5 2012
DVCon Panel: Will Differentiation Through Software Kill Chip Design?

Will systems-on-chip (SoCs) become so expensive to design that people are going to buy chips off the shelf, and differentiate products through software alone? That's one question that was put before a panel of EDA industry experts at the DVCon conference Feb. 29, 2012. Short answer -- no, but we...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 1 2012
DVCon User Panelists: Is Low Power Design Worth the Costs?

Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 29 2012
System-Level Design and the Waves of EDA

Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago. 2011 was an interesting year for system-level design. In May Cadence announced its participation...

Posted to System Design and Verification (Weblog) by fschirrmeister on Mon, Jan 30 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design

Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 22 2012
Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for the Zynq-7000 EPP . The FPGA world has changed a lot from 1995 when I was an FAE at Cypress Semiconductor selling and supporting programmable logic devices. This was during the transition from schematic capture to HDLs...

Posted to System Design and Verification (Weblog) by jasona on Fri, Oct 28 2011

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software

System-Level Low Power Design – What Will it Take to Move There?

Is System Modeling the Next EDA Abstraction Level?

Trying to Make Sense of the Chaos – Impressions from Design West 2012

EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More

Differentiation Through Hardware is Not Going Away

DVCon Panel: Will Differentiation Through Software Kill Chip Design?

DVCon User Panelists: Is Low Power Design Worth the Costs?

System-Level Design and the Waves of EDA

Q&A: Frank Schirrmeister Updates Status of System-Level Design

Welcome to the Zynq-7000 Virtual Platform