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software-driven verification,verification

  • DVCon 2014: How to Close the Verification Gap

    SAN JOSE, Calif.--Sometimes in the electronics industry, the best questions are at once the simplest and scariest. Consider the one raised in a DVCon 2014 panel (Richard Goering blogged in detail here ): Have we created the verification gap? I invited Cadence Senior Architect JL Gray and ChipDesign Magazine...
    Posted to The Fuller View (Weblog) by Brian Fuller on Thu, Mar 20 2014
  • Software-Driven Verification – a Hot Topic for 2013?

    Many engineers today use C language software running on an embedded processor model to build testbenches for hardware verification. This "software-driven verification" technique is an ad-hoc methodology that often uses home-grown tools. But it's something you may hear more about in 2013...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 3 2013
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