Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
The Fuller View Blog
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> skill
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
The Fuller View Blog
All Blog Categories
Popular Tags
Allegro
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
IP
Low power
mixed-signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
skill
16.3
16.5
5.1.14
ADE
ADE-XL
Allegro
Allegro PCB Editor
Allegro Skill
Analog
AXL
axlDBCreateShape
Cadence
Cadence SKILL
callback
CDNlive
cdsenv
change layers
classes
closures
ConceptHDL
config
copy
create path
create via
custom
Custom IC Design
customization
database objects
dbcreatevia
deRegUserTriggers hiDeleteMenu deUnRegUserTriggers Banner Menu
drc
Gerber
gui
hierarchy
IBIS
IC 6.1.5
IC615
icfb
Industry Insights
Jim Newton
layer functions
layout
LISP
loading files
Monte Carlo
multipart path
netlisting
object orientation
ocean
OCEAN script
OCEAN scripting
Oceanscript
OpenPDK
OrCAD Capture Marketplace
OrCAD PCB Editor
padstack
PCB
PCB Layout and routing
PCB SKILL
pcell
pcell instance
PCells
PDK
PDKs
Popup Menu
procedure
programming
properties
Python
rod
ruler
save
Schematic
scripts
Si2
skil code
Skill Code
skill code or command
SKILL database attribute documentation
SKILL for the Skilled
skill form
SkiLL form gui
skILL form pcb form
skill function
SKILL multipartpaths
Skill programming
Skill script
skill++
software development
Sudoku
sum a list
summing
Team SKILL
triggers
update
via
Virtuoso
Virtuoso 6.1.5
Virtuoso Analog Design Environment
Virtuoso IC6.1.5
schViewToView
Hi all, I want to write a skill file to update standard cell librarie all symbols with VDD/VSS pins. There exits all symbol view. When I use the "schViewToView()" function, I want to select the "Modify" function. How could I do the job automatically? Thanks for your great help! Best...
Posted to
Custom IC SKILL
(Forum)
by
geeknerd
on Mon, Dec 24 2012
Manipulating a single Instance Iterations in Virtuoso
I am trying to manipulate the parameters of a single instance of an array (I1<1024:1>). The instances contain a simple RC network and a current source modelling a rather complex circuit. All the instances are connected in series using a bus-notation. Now I need to add a unique delay to every single...
Posted to
Custom IC Design
(Forum)
by
Battosai
on Wed, Dec 12 2012
Adding description for the formal arguments in SKILL PCell
I wish to add description for the formal arguments I have in my Skill Pcell code . And I want the description to be displayed in the edit form whenever the pcell is queried along with the arguments. What is the easiest way of doing it ?
Posted to
Custom IC Design
(Forum)
by
Liji
on Wed, Dec 5 2012
SKILL for the Skilled: Part 5, Many Ways to Sum a List
In the most recent posts of SKILL for the Skilled (see previous post here ) we looked at different ways to sum a given list of numbers. The goal of these articles is not really to help you sum lists better, but rather to use a simple problem to demonstrate and compare features of the SKILL++ language...
Posted to
Custom IC Design
(Weblog)
by
Team SKILL
on Mon, Nov 26 2012
Re: How to Update a custom Menu using a Menu item without deUnRegMenuTriggers()
Hello, I am using the folowing code to use a menu item to update the menu contents and functions but it is not working properly. Using the Update item, I see all the right messages in the CIW, stating that functions have been redefined, but the functions do not really update (operate according to updated...
Posted to
Custom IC SKILL
(Forum)
by
jaleco
on Tue, Nov 6 2012
Re: Slotted Metal paths
Hi Lawrence, thanks for your reply and thank you for the script. I agree about the age of the code. I was hoping there might have been some update to it based on its age and the ubiquitousness of the application. I would like to enhance the form input to accept user defined bus widths without limitation...
Posted to
Custom IC SKILL
(Forum)
by
jaleco
on Mon, Nov 5 2012
Slotted Metal paths
Does anyone know of an updated version of the CCSslotMetal.il script for slotted metal paths? This code is very old and has little flexibility for things like defining the size of the slots, width of the path, etc.
Posted to
Custom IC SKILL
(Forum)
by
jaleco
on Mon, Nov 5 2012
How to Unregister a custom Menu using deUnRegUserTriggers()
Referencing an old post by Andrew Beckett, (Andrew if you could please clarify how to do this) http://www.cadence.com/Community/forums/p/17476/1245483.aspx#1245483 I am trying to build a menu which includes a menu item to re-load the menu. The purpose is for adding new items and for testing and debugging...
Posted to
Custom IC SKILL
(Forum)
by
jaleco
on Fri, Nov 2 2012
Re: dbLayerTile need help
Is there any comamnd in skill which splits a polygon into max of 2 rectangles. I am writing a skill code which needs stretch all the poly gates by fixed distance and hence entire layout should move accordingly maintaining others shapes like contacts lengts/widths as constant..can anyone help me of how...
Posted to
Custom IC Design
(Forum)
by
prandi
on Tue, Oct 16 2012
Allegro Design Entry HDL SKILL Copy Schematic Page
Hello everyone. I'm a new cadence user and i've been using it for almost a week now. I wanted to jump right into writing SKILL script to do a simple task but after reading a the manual and being overloaded with lots of SKILL commands in the user reference guide, i must admit, i'm a bit discouraged...
Posted to
PCB SKILL
(Forum)
by
burningslash
on Tue, Oct 2 2012
Page 3 of 28 (275 items)
< Previous
1
2
3
4
5
Next >
...
Last ยป