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  • Archived Webinar: Bringing SystemC and C/C++ Models into UVM

    If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 7 2011
  • SimVision Assertions

    I have an assertion along the lines of : assert property( @(posedge clk) A |-> B ); When I run this on Cadence, I get that the assertion failed. Looking at the waveform (counter example), it shows that when A occurs on the negedge of the clock, Cadence is still checking to see if B happened. And when...
    Posted to Functional Verification (Forum) by pdar on Fri, Jul 29 2011
  • Transaction tracing in simvision

    Hi, I'm using OVM transaction level tracing in SV. I was wondering if I can have simvision render different types of transactions with different colors e.g. based on a transaction attribute. I know how to do it at signal level using mnemonics but I haven't succeeded doing this at transaction...
    Posted to Functional Verification (Forum) by Joep Boonstra on Sun, Mar 29 2009
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