	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

simulation,Debug

Develop for Debugability – Part 1

Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Apr 8 2013
Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year

Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA, Lip-Bu Tan and Cadence are also finalists for ACE Executive of the Year and Company of the Year, respectively...

Posted to Functional Verification (Weblog) by Karnane on Mon, Mar 25 2013
Using the ‘restore -append_logs' Feature

As described in Specman Advanced Option appnote , Specman Elite supports dynamic load and reseeding. This allows the user to run the simulation up to a certain point (often until right after reset) and save the simulation. The user can then restore the simulation and run many different tests either by...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Feb 12 2013
DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...

Posted to Functional Verification (Weblog) by teamspecman on Thu, Feb 7 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing

In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 16 2013
Webinar Report: Speeding RTL and Gate-Level Simulation

Every verification team wants faster functional verification performance. Fortunately, there are many ways to achieve that. A recently archived Cadence webinar illustrates a number of techniques for speeding both RTL and gate-level simulation, including "out of the box" improvements to the...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 13 2012
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...

Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 29 2012
A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help? Knowing that this customer compiles their e code, and...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Aug 15 2012
User View: Why and How to Use Transaction-Based Acceleration

Transaction-based acceleration can speed up simulation hundreds of times, but you need to develop a good strategy to take full advantage of it, according to a paper authored by Cadence and Broadcom and presented at the recent DVCon conference . The paper detailed Broadcom's experience using transaction...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 23 2011
The Increasing Role of SystemC in System Design

Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on. As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineers with many different backgrounds. Every so often...

Posted to System Design and Verification (Weblog) by jasona on Tue, Feb 22 2011

Page 1 of 2 (11 items) 1 2 Next >

Popular Tags

Email

Share

Subscribe

Contact Us

simulation,Debug

Develop for Debugability – Part 1

Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year

Using the ‘restore -append_logs' Feature

DVCon 2013 for the Specmaniac

Functional Verification Survey -- Why Gate-Level Simulation is Increasing

Webinar Report: Speeding RTL and Gate-Level Simulation

Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

User View: Why and How to Use Transaction-Based Acceleration

The Increasing Role of SystemC in System Design