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signoff,placement

  • ARM TechCon: Inside Story of a 14nm FinFET Tapeout

    The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
  • “In Design” DFM Signoff – the Inside Story

    As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
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