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signoff,Extraction,Cadence

  • Taming the Challenges of IC Design

    AUSTIN, Texas--You want the bad news first or the good news about IC design challenges? Let's start with the bad news: As IC design moves into 20nm and 16nm nodes, the challenges facing not only designers but EDA vendors are extraordinary if the industry is to maintain momentum and design productivity...
    Posted to The Fuller View (Weblog) by Brian Fuller on Wed, Jul 24 2013
  • Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

    Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff Solution . Tempus provides up to an order of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 28 2013
  • ARM TechCon: Inside Story of a 14nm FinFET Tapeout

    The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
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