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signal integrity,encounter

  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • Mixed Signal Technology Summit Proceedings Now Available

    In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
    Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
  • DFM issues

    Dear Brian Hope you are doing fine and well , I would just like to learn a few more tips (with your help of course). 1. I am trying to put multiple vias on metal contacts. 2. I also want to increase the width of the metal wires by defining a "Non-Default-Rule" in the encounter tool . Both these...
    Posted to Digital Implementation (Forum) by BraveHeart on Sat, Jul 28 2012
  • Five-Minute Tutorial: Fixing SI Victim Nets

    It's hard to believe there was a time when we didn't even run signal integrity analysis. It wasn't always a necessity at the larger nodes of several years ago, but it's absolutely essential in today's processes. So I'm sure every one of you out there has battled SI violations...
    Posted to Digital Implementation (Weblog) by Kari on Wed, May 18 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • ARM, Cadence Webinar: How SOI Impacts Timing and Signal Integrity

    You probably know that silicon-on-insulator (SOI) technology offers lower power and/or better performance than bulk CMOS, and that qualified IP libraries are available. But what's the impact on the digital design flow? Fairly minimal, but there are a few things you need to know about timing and signal...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 30 2010
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