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signal integrity,Functional Verification

Mixed Signal Technology Summit Proceedings Now Available

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...

Posted to Mixed-Signal Design (Weblog) by nizic on Thu, Dec 13 2012
Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: --------- o Rerun the same test with the same seed in...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 17 2012
AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse. While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders of the verification engineer. With Amiq's...

Posted to Functional Verification (Weblog) by Team genIES on Fri, Jan 8 2010
Simulation of Voltage Scaling for Dynamic Power Reduction

Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction. RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings...

Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 22 2009
Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

Some background info: Taking a quick look at Power dissipation in CMOS: Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator) using CPF (Common Power Format) commands to capture...

Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 15 2009

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signal integrity,Functional Verification

Mixed Signal Technology Summit Proceedings Now Available

Analyzing Error Reports When Specman Crashes

AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

Simulation of Voltage Scaling for Dynamic Power Reduction

Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction