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sensitivity analysis,Virtuoso

  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Archived Webinar: Variation-Aware Analysis for Advanced Node Design

    Why is variation such a big problem at 45nm and below, and what can custom/analog designers do to analyze and mitigate it? A new series of Cadence webinars on "variation-aware design" helps answer these questions. This blog post reviews the first webinar in the series, which was offered Nov...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Nov 11 2012
  • Effect of load capacitor at the output of an oscillator

    Hi, While designing an oscillator ,which had a ring oscillator(differential ended) architecture , the frequency sensitivity of the vco had changed, that is if initially my vco works in a frequency range of 300MHz - 500MHz aor a control voltage range (1.3V-1.85V). After adding a capacitor at the output...
    Posted to Custom IC Design (Forum) by Jithin on Thu, Apr 12 2012
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
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