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  • Re: Doubt regarding SDF

    Thanks kari, But I have one doubt regarding this. I've used same max,min and typical lib for both encounter and ETS. So delay for each standard cells same in both encounter and ETS. Then Why we go for ETS to write sdf and timing optimization? If I'm wrong,correct me. Thanks, selvam.
    Posted to Digital Implementation (Forum) by selvam27 on Wed, Mar 13 2013
  • Whitepaper Review: Improving Gate-Level Simulation Performance

    As I wrote in a January 2013 blog post , a recent Cadence customer survey confirmed that gate-level simulation usage is increasing, and that it can potentially take up to one-third of the simulation time and over half the debugging time. Since gate-level simulation is much slower than RTL simulation...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Feb 18 2013
  • SDF generation in Encounter

    I have a problem generating SDF file in encounter. The problem is that the generated SDF file only includes delay information for the interconnects but not the gates. Here is how I generated the SDF file: I have a standard cell library containing all the required cellviews (i.e. schematic, symbol, layout...
    Posted to Digital Implementation (Forum) by 01farhad10 on Sun, Aug 26 2012
  • User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

    Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
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