Home > Community > Tags > rtl compiler/power analysis/synthesis
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

rtl compiler,power analysis,synthesis

  • Does clock power included in Power Report ?

    Hi All, I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and then using "report power" command, however when RC loads the VCD file it shows...
    Posted to Logic Design (Forum) by dkhan on Sat, Jul 27 2013
  • Re: gray code

    Hi gh-, RTL Compiler has no support to control FSM coding style. I vaguely remember even Synplify had a pragma for this (binary, one-hot, gray or Johnson coding). I have done an experiment: Synthesized 9-bit binary counter, and then synthesized 9-bit Gray counter (using CW_cntr_gray) using following...
    Posted to Digital Implementation (Forum) by Sporadic Crash on Mon, Oct 29 2012
  • Synthesis User Panel: Power Dominates Front End Design

    What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011
Page 1 of 1 (3 items)