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rtl compiler,power analysis

  • Re: Does clock power included in Power Report ?

    [quote user="grasshopper"] Hi dkhan, unfortunately the answer is "It depends" If you are using a netlist and also annotating all parasitics, you will effectively have the clock tree accounted for but if you do not annotate parasitics or working at RTL level, the answer is mostly not...
    Posted to Logic Design (Forum) by dkhan on Mon, Jul 29 2013
  • Does clock power included in Power Report ?

    Hi All, I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and then using "report power" command, however when RC loads the VCD file it shows...
    Posted to Logic Design (Forum) by dkhan on Sat, Jul 27 2013
  • using ModelSim/QuestaSim VCD file in RTL compiler

    Hi, I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports...
    Posted to Logic Design (Forum) by dkhan on Tue, Jun 18 2013
  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
  • Problem occurs when reading vcd in RTL Compiler

    Dear all, I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files: gcm.v (This is the main circuit. Module name is "gcm") tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb"...
    Posted to Logic Design (Forum) by rexnyu on Tue, Mar 26 2013
  • Re: gray code

    Hi gh-, RTL Compiler has no support to control FSM coding style. I vaguely remember even Synplify had a pragma for this (binary, one-hot, gray or Johnson coding). I have done an experiment: Synthesized 9-bit binary counter, and then synthesized 9-bit Gray counter (using CW_cntr_gray) using following...
    Posted to Digital Implementation (Forum) by Sporadic Crash on Mon, Oct 29 2012
  • Synthesis User Panel: Power Dominates Front End Design

    What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011
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