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rtl compiler,power analysis

  • Problem occurs when reading vcd in RTL Compiler
    Dear all, I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files: gcm.v (This is the main circuit. Module name is "gcm") tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb"...
    Posted to Logic Design (Forum) by rexnyu on Tue, Mar 26 2013

  • Re: gray code
    Hi gh-, RTL Compiler has no support to control FSM coding style. I vaguely remember even Synplify had a pragma for this (binary, one-hot, gray or Johnson coding). I have done an experiment: Synthesized 9-bit binary counter, and then synthesized 9-bit Gray counter (using CW_cntr_gray) using following...
    Posted to Digital Implementation (Forum) by Sporadic Crash on Mon, Oct 29 2012

  • Synthesis User Panel: Power Dominates Front End Design
    What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011
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