Home > Community > Tags > rtl compiler
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

rtl compiler

  • Re: how to remove constant value flops?

    Hi grasshopper: Thx for your reply. The IP has multi AHB master ports, we remove 1 master so one of the AHB master ports related signals are all tied to 0 (ex: AHB7_HCLK, AHB7_HRESETN....) I think there maybe some input ports related to those registers are not tied at 0. But what I am curious is that...
    Posted to Digital Implementation (Forum) by tompy on Wed, Jun 23 2010
  • how to remove constant value flops?

    Hi : I got an IP from vendor. Due to design change, some part of the IP are not needed. Since it is time consuming to ask the vendor to remove those flops, I wish to do it in synthesis. I tied the unused part IP clock port and reset_n port to 0. And I want RTL compiler remove those unclocked/always reset...
    Posted to Digital Implementation (Forum) by tompy on Wed, Jun 23 2010
  • TSMC Reference Flow Adds TLM Support -- Here's Why

    Every year as spring turns to summer, we can count on a new Reference Flow from TSMC. While the seasons are driven by the laws of nature, the Reference Flow is driven by the laws of Moore. Typically the new additions to the flow have to do with accounting for new process effects such as signal integrity...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Jun 11 2010
  • Cadence SOC Encounter 7.1 and 8.1 - keyboard not working

    My SOC installation does not respond to any commands from keyboard (looks like keyboard do not exist) So i run in severe problems because can not edit synthesis scripts etc. All other software, including Cadence IC, is working properly. My system is CentOS 5.4, 64 bit. I use Japanese USB keyboard. Any...
    Posted to Digital Implementation (Forum) by trurle on Wed, May 19 2010
  • Friday Fun: Multi-objective optimization for your iteration problem

    Here in the U.S., in recent years we've seen all kinds of commercials on TV for prescription pharmaceuticals. Needless to say, they have to figure out how to sell something that is very intangible in most cases. This is not unlike algorithm-oriented EDA software! So we decided to have some fun and...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Apr 16 2010
  • Why physical guides are like Kramer

    There has been a lot of talk recently about improving synthesis predictability by passing forward "guides" to physical design. This was something that we investigated doing in RTL Compiler, too. That was 2003. So whenever I get asked by folks if we would consider a similar approach in RTL Compiler...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Apr 12 2010
  • RTL compiler - elaborate problem.

    Hi All, When I run rtl compiler I am facing the following error: Error : Invalid operating_conditions name. [LBR-32] [elaborate] : Library has no operating conditions named 'tt_1p2v_25c'. : Use ls to see the valid operating_conditions in the libraries. Error : Error when processing libraries...
    Posted to Digital Implementation (Forum) by sandeepsuhas on Thu, Mar 11 2010
  • When Will We Move From RTL to TLM? I Need to Know!

    My esteemed colleague, Steve Brown, recently wrote a well-thought piece trying to forecast what it will take to move the bulk of design from RTL abstraction to transaction-level modeling (TLM). He uses the gate-level to RTL migration as a reference point so that we can learn from history. He lists a...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Mar 8 2010
  • Q&A: How System Design And Verification Can Go “Mainstream”

    System design and verification are part of the RTL flow today, but a higher level of abstraction is now poised to enter the IC design mainstream, according to Ran Avinun, marketing group director for system design and verification at Cadence. In this interview he discusses trends in hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Feb 18 2010
  • RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

    I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Jan 25 2010
Page 9 of 13 (121 items) « First ... < Previous 7 8 9 10 11 Next > ... Last »