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rtl compiler,Synthesis

  • how to identify unique nets connected to preset/clear pins of all FFs in a scope

    I have not been able to find an attribute that shows whether a net in a scope is connected to a preset/clear of FF. The only way I have found: foreach FF in a scope { foreach pin of this FF { if { libpin of this pin is a {async_clear} } { set an async_clear net } if { libpin of this pin is a {async_preset...
    Posted to Logic Design (Forum) by Sporadic Crash on Tue, Jan 7 2014
  • Front-End Design Summit: The Future of RTL Synthesis and Design for Test

    You don't hear much about RTL synthesis or design for test (DFT) these days, probably because many people think these are long-solved problems. But according to speakers at the Cadence Front-End Design Summit Dec. 5, 2013, both RTL synthesis and DFT are rapidly evolving to keep up with the demands...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 10 2013
  • Steps to perform Place & Route from Synthesized Netlist

    Hi, I have a synthesezed netlist of my design (*.v file) and now I want to perform place & route as well inorder to determine more accurate timing results. I would like to know how P&R can be done with default constraints just to get a rough timing estimate. I have *.lib and *.lef library files...
    Posted to Digital Implementation (Forum) by dkhan on Wed, Oct 2 2013
  • Does clock power included in Power Report ?

    Hi All, I am conserned whether my power reports include clock power or I have to calculate it separately. Currently I am defining clock period using "define_clock" command before loading my Netlist and then using "report power" command, however when RC loads the VCD file it shows...
    Posted to Logic Design (Forum) by dkhan on Sat, Jul 27 2013
  • RTL compiler command for retaining design hierarchy

    Hi, Is there a command in RTL compiler which can force the synthesizer to retain original hierarchy of the design, like there is in Xilinx ISE for instance? Thanks.
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • How to avoid unwanted removal of logic during synthesis

    Hi All, I am synthesizing a processor design with RTL compiler. The synthesized netlist works fine and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL compiler meets the constraint...
    Posted to Logic Design (Forum) by dkhan on Sun, Jul 7 2013
  • Videos, Presentations Highlight Front-End IC Design Methodologies

    Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations and videos from most of the sessions are...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 9 2013
  • Virtual Clock and Synthesize :)

    Hi everyone, I have couple of doubts. Please help me out. 1. My project is about SRAM design controller. While doing compilation i can able to see(in GUI) all my modules in my design but when i synthesize it one of the sub-module(Adress Decoder-FSM module) is not available. What will be the reason for...
    Posted to Digital Implementation (Forum) by Ram S on Sat, Mar 16 2013
  • Re: gray code

    Hi gh-, RTL Compiler has no support to control FSM coding style. I vaguely remember even Synplify had a pragma for this (binary, one-hot, gray or Johnson coding). I have done an experiment: Synthesized 9-bit binary counter, and then synthesized 9-bit Gray counter (using CW_cntr_gray) using following...
    Posted to Digital Implementation (Forum) by Sporadic Crash on Mon, Oct 29 2012
  • Re: gray code

    I am interested in Gray coding with RTL Compiler. In the tool following synthetic operators are used: BIN2GRAY_STD_LOGIC_OP, GRAY2BIN_STD_LOGIC_OP, INC_GRAY_STD_LOGIC_OP Additionally, following ChipWare components are related to Gray codes. CW_inc_gray, CW_gray2bin, CW_cntr_gray, CW_bin2gray There is...
    Posted to Digital Implementation (Forum) by Sporadic Crash on Wed, Oct 24 2012
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