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rtl compiler,Industry Insights

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest"...

Posted to Industry Insights (Weblog) by rgoering on Tue, Nov 27 2012
Designer View – Low-Power IC Design Challenges and Solutions

The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 23 2012
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction except for some high-end CPU server and networking...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 10 2012
The Technology Behind Encounter 11.1 – Physical Aware Front End Design

In my last blog post I discussed new optimization and modeling technology in the Encounter 11.1 release, announced by Cadence March 5. While that blog post focused on physical IC ("back end") design, the new release also brings more "physical awareness" to front-end design, and that's...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 6 2012
User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 5 2012
Synthesis User Panel: Power Dominates Front End Design

What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011
How Logic Synthesis is Changing

You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 14 2011
Design for Test (DFT) – New Challenges at Advanced Process Nodes

Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. To...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 15 2011
How Imec and Cadence “Wrapped Up” 3D-IC Test

One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 1 2011

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rtl compiler,Industry Insights

Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

ARM Blog Tells Story of a 20nm Cortex-M0 Test Chip

Designer View – Low-Power IC Design Challenges and Solutions

Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

The Technology Behind Encounter 11.1 – Physical Aware Front End Design

User View: “Multi-Mode” Synthesis Approach Includes Power Optimization

Synthesis User Panel: Power Dominates Front End Design

How Logic Synthesis is Changing

Design for Test (DFT) – New Challenges at Advanced Process Nodes

How Imec and Cadence “Wrapped Up” 3D-IC Test