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  • RC - read_hdl

    Hi Everyone, When reading verilog (read_hdl -sv), first file is common variable definitions (like `define and localparam). There is no problem loading this file, however when loading the actual RTL design it cannot recognize the mentioned above variables (Error - undeclared). If the same variable definitions...
    Posted to Logic Design (Forum) by Yemelya on Wed, Jul 31 2013
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