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power,Industry Insights,3D IC

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 23 2013
Q&A: Jiayuan Fang Discusses Sigrity, Cadence Merger, Signal and Power Integrity, and 3D-ICs

In July 2012 Cadence announced its acquisition of Sigrity , a leading provider of signal integrity (SI) and power integrity (PI) analysis tools for chip, package and board. Jiayuan Fang, Sigrity founder and CEO, joined Cadence as vice-president of R&D for high-speed design products in the Silicon...

Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 12 2012
Si2 DAC Panel: What Standards are Needed for 3D-ICs?

3D-ICs with through-silicon vias (TSVs) are not yet in volume production, but work has already begun on design standards - and more work is needed soon. An excellent update on work in progress, and a discussion of what's needed, was provided at a Silicon Integration Initiative (Si2) panel discussion...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 28 2012
Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011

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power,Industry Insights,3D IC

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

Q&A: Jiayuan Fang Discusses Sigrity, Cadence Merger, Signal and Power Integrity, and 3D-ICs

Si2 DAC Panel: What Standards are Needed for 3D-ICs?

Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs