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power management,power estimation

  • Panelists: Low Power Design Needs System-Level Boost

    When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 28 2012
  • DVCon User Panelists: Is Low Power Design Worth the Costs?

    Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 29 2012
  • Logic Design and Test Design: Do they need each other?

    Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important...
    Posted to Logic Design (Weblog) by Ed JM on Sat, Apr 17 2010
  • Power Management for Test: A Means of Addressing False Failures

    Engineering teams are tracing test failures back to IR/voltage drop during test mode. These false failures are impacting yield, profitability. We consider this to be a power management issue for test mode and should be approached as early as front-end design and carried through ATPG and pattern/vector...
    Posted to Logic Design (Weblog) by Ed JM on Thu, Oct 23 2008
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