Home > Community > Tags > power intent/constraint
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

power intent,constraint

  • Is Power A Constraint?

    As I’ve mentioned, I have done chip design for many years. And one thing I learned early was the concept of Golden RTL – the idea that the final chip netlist MUST match the final RTL. Now, this can lead to certain anal-retentive behaviors. One rule we had was if we had to modify the RTL late...
    Posted to Logic Design (Weblog) by Rich Owen on Mon, Oct 6 2008
Page 1 of 1 (1 items)