Home > Community > Tags > power integrity/16.6
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

power integrity,16.6

  • Keep power nets separate in a hiearchical design

    Hello, Say that I instantiate the same block four times in a schematic, I’m using the SUBDESING_SUFFIX attribute to keep the same location value in each instance, for example, R1 becomes R1CH1 in channel 1, R1CH2 in channel 2 and so forth. Even though all four blocks are identical I want to use...
    Posted to PCB Design (Forum) by Mattias J on Wed, Jun 4 2014
  • PDN Analysis Static IR drop sim fails

    I'm experimenting with PDN analysis on a trivially simple design (2 DC sources, 4 caps and 1 load resistor). Static IR drop analysis fails with this log message: 10:46:04: Parse all pin shape short ... 10:46:04: Parsing static model for all power/ground/signal traces... 10:46:05: Generating static...
    Posted to PCB Design (Forum) by JMinCV on Wed, Jul 17 2013
Page 1 of 1 (2 items)