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power gating,power domain

  • CTS for design with multiple power domains

    Hi, I have a power gated domain that I'm trying to implement that I'm having trouble with CTS. I have 2 power domains : base_domain(always on) and gated_domain(power-gated). Both domains have multiple clocks in the domains that I'm trying to synthesize clock tree for. For some reason, when...
    Posted to Digital Implementation (Forum) by fieldy on Thu, Jan 30 2014
  • optDesign command in SoC Encounter

    Hi all, I was wondering if there is a way to disallow the movement of cells by the optDesign command in SoC Encounter. I have two power domains, where one power domain contains cells that are power gated (rails are virtual vdd and gnd) and the other power domain has nominal supply. However, when I run...
    Posted to Digital Implementation (Forum) by Northfork on Sun, Apr 21 2013
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