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power gating,low-power design,low-power

  • What’s Cool for Low-Power at DAC?

    Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 30 2012
  • Low-Power Design? Brian Bailey Gets It

    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • Does Substrate Biasing Have a Future?

    At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more...
    Posted to Low Power (Weblog) by Pete Hardee on Mon, Feb 6 2012
  • ARM Keynote: Some Inconvenient Truths About Low-Power Design

    While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 17 2011
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