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power gating,Encounter

  • CTS for design with multiple power domains

    Hi, I have a power gated domain that I'm trying to implement that I'm having trouble with CTS. I have 2 power domains : base_domain(always on) and gated_domain(power-gated). Both domains have multiple clocks in the domains that I'm trying to synthesize clock tree for. For some reason, when...
    Posted to Digital Implementation (Forum) by fieldy on Thu, Jan 30 2014
  • UltraSim simulation issue for Power-up Rush Current Analysis with Power Gate(Switch)

    Hi All, I'm trying to run a rush current Analysis for a power-gated design I am implementing. I've been going through the Encounter and EPS manual to set the analysis up properly and I don't think I'm doing anything wrong...But whenever I run the power-up (rush current) analysis, EPS...
    Posted to Digital Implementation (Forum) by fieldy on Wed, Sep 25 2013
  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • Video, Presentation – Low Power Design with ARM Physical and Processor IP

    Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 17 2012
  • Does Substrate Biasing Have a Future?

    At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more...
    Posted to Low Power (Weblog) by Pete Hardee on Mon, Feb 6 2012
  • How Easy Is It to Switch Off Power?

    How easy is it to switch off power? "Honey, could you please make sure all the lights are off before going to bed?" Although I am always wondering why I have to be one to do this, I do not have too many complaints as it is a job of simply flipping a switch. Low power designers wish that designing...
    Posted to Low Power (Weblog) by QiWang on Thu, Apr 14 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
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