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power estimation,Cadence

  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
  • Panelists: Low Power Design Needs System-Level Boost

    When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 28 2012
  • DVCon User Panelists: Is Low Power Design Worth the Costs?

    Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 29 2012
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