Home > Community > Tags > power estimation
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

power estimation

  • Power Difference between Analog Simulation and RTL complier estimation
    Hallo, I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc. Now based on that I created library file, and used that in RTL omplier for single cell designs...
    Posted to Logic Design (Forum) by GreenGraphene on Mon, Mar 25 2013

  • Panelists: Low Power Design Needs System-Level Boost
    When low-power design experts get together, much of the conversation turns to the system level. At least that was the case at the recent Low Power Technology Summit held at Cadence Oct. 18, 2012, where audience members questioned panelists about early power estimation, power modeling, and the role of...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Oct 28 2012

  • DVCon User Panelists: Is Low Power Design Worth the Costs?
    Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 29 2012

  • User View: Low Power Challenges at 40nm and Below
    Low power design is hard enough at 65nm and above, and it poses additional challenges at 40nm and below, according to Alex Kuo, department manager at SoC design firm Global Unichip Corp. As noted in another Cadence Community blog post by Qi Wang, Kuo offered a presentation on low-power design at the...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 21 2011

  • Logic Design and Test Design: Do they need each other?
    Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important...
    Posted to Logic Design (Weblog) by Ed JM on Sat, Apr 17 2010

  • Power Management for Test: A Means of Addressing False Failures
    Engineering teams are tracing test failures back to IR/voltage drop during test mode. These false failures are impacting yield, profitability. We consider this to be a power management issue for test mode and should be approached as early as front-end design and carried through ATPG and pattern/vector...
    Posted to Logic Design (Weblog) by Ed JM on Thu, Oct 23 2008

  • Coarse PSO and the new Apple MacBook
    After a long day, I like to browse around the web, looking for interesting stories. Ok, yes, I’m a geek (as my daughter continues to remind me, accompanied by a roll of her eyes). But I found this story about the new MacBook too interesting to pass up. I agree with Seth that the most interesting...
    Posted to Logic Design (Weblog) by Rich Owen on Thu, Oct 16 2008

  • Blogs: What interests you? What do you want to read about?
    With the new blogging opportunities at Cadence, is there anything you'd like to read more about for frontend design? Stuff like: Early chip-planning/prototyping, synthesis (including physical-synthesis), formal verication, DFT, frontend methodologies, etc. My hope is for the blog topics to be informative...
    Posted to Logic Design (Weblog) by Kenneth Chang on Mon, Sep 15 2008

  • "What is ChipEstimate?" plus a touch of RC-Physical x 2
    Day 2 @ CDNLive San Jose: Another interesting day - met quite a few people, some new, others I met the day before while co-presenting at two morning sessions, and also some of my fav customers. My focus-of-the-day - ChipEstimate awareness with a touch of RC-P. Here are some attendees' feedback: Question...
    Posted to Logic Design (Weblog) by Kenneth Chang on Thu, Sep 11 2008

  • Some tips for predicting power consumption
    In my previous post , entitled “How do you predict power?”, I was actually looking for reader input via the comments. I should have been more clear on that….perhaps I am too accustomed to my 6-year-old son, who will supply a barrage of responses to even a rhetorical question. Anyway...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Aug 11 2008
Page 1 of 2 (11 items) 1 2 Next >