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pnoise

  • Pnoise analysis

    Hi, I have been designing a PLL which gives an output frequency in the range (400-500)MHz to the reference input frequency of (20-25)MHz.So for doing the pnoise analysis I have added the PSS as well as Pnoise analysis I have made the following as setup for the analysis for a frequency of 500MHz. I have...
    Posted to Custom IC Design (Forum) by Jithin on Sun, Mar 3 2013
  • How to simulate the Noise figure in Pnoise from 1 stage to another?

    Hi there, I want to simulate the Noise figure for such a setup that first a band pass filter, then sample and hold, and then follower by amplifier, and ADC and so on. Can i get the noise figure from source to each stage with Pnoise? I understand that if the output is specified with voltage of two node...
    Posted to Custom IC Design (Forum) by zcam on Fri, Sep 28 2012
  • Insufficient memory in PNOISE simulation

    I'm trying to do phase noise analysis with PSS HB and PNOISE for post layout extracted netlist. I got the following error: Mem Used: 12813.8 MB (Memory Exhausted) Fatal error found by spectre at freq = 10 MHz during PNoise analysis `pnoise'. FATAL (CMI-2002): Insufficient memory available. To...
    Posted to RF Design (Forum) by Massoud THDN on Tue, May 29 2012
  • Modeling Oscillators with Arbitrary Phase Noise Profiles

    When you need to include noisy oscillators in SpectreRF transceiver simulations, you have at least 3 options: 1) Semi-autonomous simulation is the most accurate approach, recommended whenever the transistor-level model of the oscillator is available. 2) rfLib/osc model is less accurate but it’s...
    Posted to RF Design (Weblog) by Tawna on Thu, May 24 2012
  • High frequency quadrature VCO design with good phase noise

    Hello everyone I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
  • Re: Phase Noise vs frequency graph problem

    Hello Frank, Really appreciate your help..I have put my latest schematic in this post..if you have time to have a look...I haven't used the oscillator mode in pss analysis.. I have a few other problems too which i will be posting separately.. I am having trouble getting quadrature output..i.e. the...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
  • Re: RE: Phase Noise vs frequency graph problem

    Hello Tawna, I am very thankful for your reply...Read a lot of posts by you and Andrew in various topics and a fan of your knowledge and work.. I got the correct graph yesterday when I changed errpreset to 'moderate' and putting tstab as 60n..but the values of phase noise was aroung -140dbc/hz...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
  • Re: Phase Noise vs frequency graph problem

    Thanks Frank for replying. Yes, I have seen that post-it explains the equation which spectre uses to find the pnoise...but it doesnt help me to get the right graph with negative values of pn. I am doing the pss-pnoise simulation using the following settings: PSS : Harmonic Balance beat freq - 37.93G...
    Posted to Custom IC Design (Forum) by rohan kr on Wed, Mar 28 2012
  • Phase Noise vs frequency graph problem

    Hello I am a newbie engineer starting my career in IC design and working on a high frequency oscillator (38 GHz). I am using Cadence IC6.1.5-64b.500 version and using spectre simulator for the schemtic design and simulations. I am having doubts about my 'pnoise' analysis. All the research papers...
    Posted to Custom IC Design (Forum) by rohan kr on Wed, Mar 28 2012
  • Jitter from pnoise simulation

    I'm desinnig a Time to digital converter and I would like to simulate the jitter of a driven buffer having a rising time of 350 ps. In my schematic, the buffer is driven by vpulse (ideal CLK @ 2 MHz) and I would like to simulate his output jitter. My setting of pss simulation is as follow: Beat frequency...
    Posted to RF Design (Forum) by moez on Fri, Mar 9 2012
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