Home > Community > Tags > pnoise pss vco/phase noise simulation

 Login with a Cadence account. Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register | Membership benefits
 Get email delivery of the Cadence blog (individual posts).

## Email

Recipients email * (separate multiple addresses with commas)

Message *

 Send yourself a copy

## Subscribe

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

First Name *

Last Name *

Email *

Company / Institution *

 Send Yourself A Copy

# pnoise pss vco,phase noise simulation

• #### PN function in Visualizaion & Anaysis XL Calculator

Hi, I have a question about the PN function, available in the Calculator. Is an output phase noise spectrum is a signle sideband or a double sideband spectrum? To avoid any confusions, I mean the 'double sideband' by a spectrum 3dB more than the 'single sideband' in magnitude. Thanks...
Posted to RF Design (Forum) by JaeWook on Tue, Feb 18 2014

Can anyone offer some suggestion please ??
Posted to RF Design (Forum) by rohan kr on Tue, Nov 5 2013
• #### phase noise of divider

I need to simulate the phase noise of a divider (or, more generally, simulate the phase noise on a non-sinusoidal signal). Most straightforward way is SpectreRF -> pss -> pnoise. There used to be a Cadence application Note about how to do this. I remember it had to do with simulating pnoise with...
Posted to RF Design (Forum) by Frank Opteynde on Thu, Oct 24 2013
• #### Insufficient memory in PNOISE simulation

I'm trying to do phase noise analysis with PSS HB and PNOISE for post layout extracted netlist. I got the following error: Mem Used: 12813.8 MB (Memory Exhausted) Fatal error found by spectre at freq = 10 MHz during PNoise analysis `pnoise'. FATAL (CMI-2002): Insufficient memory available. To...
Posted to RF Design (Forum) by Massoud THDN on Tue, May 29 2012
• #### Jitter from pnoise simulation

I'm desinnig a Time to digital converter and I would like to simulate the jitter of a driven buffer having a rising time of 350 ps. In my schematic, the buffer is driven by vpulse (ideal CLK @ 2 MHz) and I would like to simulate his output jitter. My setting of pss simulation is as follow: Beat frequency...
Posted to RF Design (Forum) by moez on Fri, Mar 9 2012
Page 1 of 1 (5 items)