Home > Community > Tags > placement

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

placement

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 12 2013
Introduction to Cadence Virtuoso Advanced Node Design Environment

What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology. Problems of Advanced Node Design When designing...

Posted to Custom IC Design (Weblog) by Hiro Ishikawa on Mon, Jan 28 2013
ARM TechCon: Inside Story of a 14nm FinFET Tapeout

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 31 2012
Constraining cell placement

I am looking for commands in Encounter that will group cells together in close proximity, but I can't seem to find them. The commands would be similar to magnet_placement, create_rp_group, and add_to_rp_group in IC Compiler. Can someone give me the names of the commands or a script that would have...

Posted to Digital Implementation (Forum) by Ken Stevens on Fri, Oct 19 2012
How to achieve align placement?

Hi all, I was wondering can encounter achieve align placement? Cuz I see someone's layout that cells has been placed align with the boundary, seens so nice! please tell me how to do that. Thanks. One more question, how can I add a wire without any pin. Cuz when I add a wire by (a), it says (e) first...

Posted to Digital Implementation (Forum) by QQEDA on Fri, Aug 17 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 1 2012
On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm

The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum . Following is a report...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 19 2012
ARM TechCon Paper: “Tips and Tricks” for Cortex-A15 Designs

The Cortex-A15 MPCore, ARM's most advanced processor, requires an optimized tool flow and design methodology to meet power, performance and area goals. A paper at the recent ARM TechCon conference showed how Texas Instruments, in collaboration with Cadence and ARM, successfully pioneered one of the...

Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 2 2011
Can't place parts in Orcad PCB... :-( Hint appreciated! :-)

I'm running an old Orcad Capture/PCB 16.2 - and have obviously been away from it too long! I can netlist (with the usual renaming warnings) and open the netlist in Orcad PCB. I get a (correct) list of parts when I go to Place/Manually - but there's no Quickview preview and I can't place anything...

Posted to PCB Design (Forum) by N i z e on Fri, Oct 28 2011

Page 1 of 2 (17 items) 1 2 Next >

Popular Tags

Email

Share

Subscribe

Contact Us

placement

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

Introduction to Cadence Virtuoso Advanced Node Design Environment

ARM TechCon: Inside Story of a 14nm FinFET Tapeout

Constraining cell placement

How to achieve align placement?

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm

ARM TechCon Paper: “Tips and Tricks” for Cortex-A15 Designs

Can't place parts in Orcad PCB... :-( Hint appreciated! :-)