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pins,netExpression

  • VXL pin generation of inherited nets

    Dear all, I have already looked into Solution ID: 1833291 but it does not seem to help me. I would like to know how top level schematic nets that are 1. not connected to any pins ( in top level ) 2. inherited in lower level schematic( inherited connection) treated during VXL pin generation. I have a...
    Posted to Custom IC SKILL (Forum) by cmohan on Wed, Jul 27 2011
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