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pins

  • Assura LVS for Standard Cell Library with only Abstract View

    Hi everyone, I am trying to perform an LVS run with a block which is streamed in from Encounter and a simple custom inverter layout which is drawn by me. My standard cell library contains cells with abstract views, therefore I need to use black box technique. I am using a simple CDL netlist for this...
    Posted to Custom IC Design (Forum) by alperro on Sat, May 17 2014
  • netlist pin order for LVS

    Hi, I'm trying to change the order in which a circuit is netlisted for LVS but I got into problems. I've modified the termOrder in the CDF form accoding to the pin order I want and I've place the following line in ~/.simrc (and also in my cadence working dir): auCdlCDFPinCntrl=t I've...
    Posted to Custom IC SKILL (Forum) by NcfC on Thu, Mar 6 2014
  • LVS assura error "Unbound Pin"

    Hi, I'm currently completing my first layout, and getting errors on all my pins. When I run LVS I am getting an error on each saying "Unbound Pin". I have simply placed the pins that were automatically generated in layout XL (when I generated the layout from schematic) within the appropriate...
    Posted to Custom IC Design (Forum) by KipD on Tue, Feb 4 2014
  • Re: Mapping a 'cv~>prop' array with any other array

    Hi Ted Thanks for the help but when I tried ur following code, in that every label in the txtObjs array becomes equal to the newLabel. I tried this :- A set of pins were selected => A<0> A<1> A<2> After which I wrote the following code txtObjs = geGetSelectedSet() => (" a...
    Posted to Custom IC Design (Forum) by shazzy on Thu, Aug 15 2013
  • Mapping a 'cv~>prop' array with any other array

    A set of selected pin labels are put into a list by doing :- cv=geGetSelSet() cv~>theLabel => ("A<0>" "A<1>" "A<2>") Another array after some operation increments the set of these pin labels by 3, i.e. :- a = ("A<3>" "A<4>"...
    Posted to Custom IC Design (Forum) by shazzy on Wed, Aug 14 2013
  • String operations in skill

    Okay so we have a list 'p' constituting of elements as pin names. p = (" GIO< 0 >" "G1E< 1 >" "GAE2< 2 >" "G3F1< 3 > ") And the task is to add the under-braces numeric value with 4 and convert this array into p = (" GIO<...
    Posted to Custom IC SKILL (Forum) by shazzy on Tue, Aug 13 2013
  • pins visible but pin names invisible in instance in layout/layout XL

    We have a problem in 5.1 layout or layout XL that some of the pins we put in our layout (at the top level of a large design) do not show visible names when we instance the cell at the next level up and hide the insides (using ^f), even after turning on the editor display options "instance pins"...
    Posted to Custom IC Design (Forum) by tdtg on Fri, Nov 2 2012
  • VXL pin generation of inherited nets

    Dear all, I have already looked into Solution ID: 1833291 but it does not seem to help me. I would like to know how top level schematic nets that are 1. not connected to any pins ( in top level ) 2. inherited in lower level schematic( inherited connection) treated during VXL pin generation. I have a...
    Posted to Custom IC SKILL (Forum) by cmohan on Wed, Jul 27 2011
  • Re: connections to abstract not verified by Assura LVS - what's wrong?

    I spoke with our foundry's support team, and I experimented some more. I finally got it working. Here's what I learned: The black box's schematic cannot be empty. It must contain at least one device (cds_thru, presistor, some transistor, etc.). If it does not, Assura LVS will prune it from...
    Posted to Custom IC Design (Forum) by TrevorB on Wed, Jan 13 2010
  • Re: connections to abstract not verified by Assura LVS - what's wrong?

    Hi Quek, Thanks for your reply. To answer your questions: 1) I cannot find the IP block's cellName even mentioned in the design.erc file. 2) The layout and schematic are both df2 - no GDS2. 3) I found the following rules in my extract.rul file: ;; ;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>...
    Posted to Custom IC Design (Forum) by TrevorB on Sat, Jan 9 2010
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