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  • Find the metal polygons having a pin

    I have some metal polygons in an instance and that is called in some other other celllview on which the pins are placed. I want to find only those the metal polygons which have pin label over them. I have written a code wherein the polygon is broken into rects and then pins are searched in the rects...
    Posted to Custom IC SKILL (Forum) by shazzy on Wed, Apr 9 2014
  • multiple pins in the same net (cds_thru layout synthesis)

    Hi, I encountered a problem with the impementation of a digital block using an RC-Encounter-Virtuoso flow. When I synthesize the block, the generated netlist/schematic uses one cds_thru block to connect two different pins to a single net. Encounter does not have any problem with this, and then generates...
    Posted to Digital Implementation (Forum) by FrancescMoll on Wed, Sep 4 2013
  • Ports mismatch

    Hi , I am running LVS, I have assigned ports in the desing but still in LVS report layout has 0 ports. I am working on Encounter10.13 dv_obj_count -transformed_nets {132639 59910} -transformed_inst {180591 116168} - transformed_port {0 423} dv_discrep 1 {Incorrect Nets} I am using the below command to...
    Posted to Digital Implementation (Forum) by Ridus on Mon, Aug 26 2013
  • Mapping a 'cv~>prop' array with any other array

    A set of selected pin labels are put into a list by doing :- cv=geGetSelSet() cv~>theLabel => ("A<0>" "A<1>" "A<2>") Another array after some operation increments the set of these pin labels by 3, i.e. :- a = ("A<3>" "A<4>"...
    Posted to Custom IC Design (Forum) by shazzy on Wed, Aug 14 2013
  • Is there a way to specify antenna info for top-level terminals?

    Hi, I'm using Encounter to build a digital block. I have placed the top-level terminals using "editPin" commands and that works fine. After building the block and integrating it with the rest of the chip (and running it through Calibre), I get antenna violations for some of these terminals...
    Posted to Digital Implementation (Forum) by FriendFX on Mon, Jun 17 2013
  • Need to place a pin on the symbol for an internal VerilogA signal

    I have an internal signal in my VerilogA code that is passed to another module, and it is not on this module's port list. But when netlisting, it complains that it wants a pin on the symbol for that signal. So my temporary solution is just to place it on the symbol and then as a no-connect on a schematic...
    Posted to Custom IC Design (Forum) by boast on Tue, May 7 2013
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