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pin names

  • Layout pin problem: net name distributes via transistor

    Hi, I am facing a problem in the layout. I designed a DRC free inverter using the gpdk90nm package from pdk.cadence. The final step of placing pins in the circuit invokes net connection errors. When the Out pin of the inverter is placed on the layout, the metal of vdd (not yet assigned) and gnd (not...
    Posted to Custom IC Design (Forum) by jeffreyprin on Fri, Sep 20 2013
  • Re: Mapping a 'cv~>prop' array with any other array

    Hi Ted Thanks for the help but when I tried ur following code, in that every label in the txtObjs array becomes equal to the newLabel. I tried this :- A set of pins were selected => A<0> A<1> A<2> After which I wrote the following code txtObjs = geGetSelectedSet() => (" a...
    Posted to Custom IC Design (Forum) by shazzy on Thu, Aug 15 2013
  • Mapping a 'cv~>prop' array with any other array

    A set of selected pin labels are put into a list by doing :- cv=geGetSelSet() cv~>theLabel => ("A<0>" "A<1>" "A<2>") Another array after some operation increments the set of these pin labels by 3, i.e. :- a = ("A<3>" "A<4>"...
    Posted to Custom IC Design (Forum) by shazzy on Wed, Aug 14 2013
  • umc 180 nm LVS with Calibre

    First I must say I must not sure if this should be asked here or Mentor's forums, anyways because I have used this forum before I will fire it up here... While using Virtuoso for custom layout on UMC 180 and trying LVS check with Calibre I have a problem with ports. In theory that should be easy...
    Posted to Custom IC Design (Forum) by soathana on Wed, Feb 13 2013
  • Skill Code to modify pin names

    I've written a skill code that is supposed to change one of the pin names of a given cell from an old value to a new one in the schematic and symbol views. It works well on the surface but gives a warning that I have to fix: the pin name gets changed as wanted in both views but there's a warning...
    Posted to Custom IC Design (Forum) by bouhoume on Tue, Nov 27 2012
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