Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> phase noise
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
phase noise
ADE
ADE XL
analog
Analog Simulation
analog/RF
APS
Cadence
cadence 6.1 virtuoso
characterization
Circuit simulation
Convergence
envelope
errset problem cadence skill
fast envelope
half fundamental frequency
Harmonic Balance
harmonic frequency
HB
HBnoise
IC6.1.5
Jitter
layout
LVS
memory
mixer
MMSIM
Monte Carlo
Monte Carlo simulation
Nand Jha
noise
noise profiles
Oceanscillator
Oscillator
phase noise simulation
PLL wizard
plot
pnoise
pnoise pss vco
post layout simulation
post-simulation
pss
QPSS Analysis
RF
RF design
RF Measurement library
RF Simulation
RF spectre spectreRF
RFIC
shooting newton
simulation
Spectre
Spectre AppNotes
Spectre RF
spectreRF
SpectreRF tutorials
strong inversion
Ted Blank
Texas Instruments
TI
transient noise analysis
Trasient Noise
tstab
VCO
Virtuoso
Virtuoso Spectre
Virtuoso Spectre Simulator GXL
Virtuoso Spectre Simulator XL
Weak inversion
SpectreRF AppNotes and Tutorials....Still One of our Best Kept Secrets!
Some of you may remember the blog written several years ago " Shhhhh...SpectreRF Tutorials and AppNotes - One of Our Best Kept Secrets ". Well, the more things change...the more things stay the same! The location of these tutorials and appNotes still seems to be one of our best kept secrets...
Posted to
RF Design
(Weblog)
by
Tawna
on Mon, Jan 16 2012
Q&A: TI Wireless Team Describes Advanced Phase-Noise Characterization for RF Oscillators Using SpectreRF
In this interview, members of the Texas Instrument wireless group talk about the characterization effort initiated and completed last year between Cadence and IBM using TI RF designs as a pilot. The goal between the two teams was to optimize SpectreRF usage to successfully and efficiently simulate TI...
Posted to
RF Design
(Weblog)
by
helenet
on Wed, Jun 15 2011
Jitter in Strong and Weak Inversions
Dear all, I have designed a crystal oscillator, but some doubts still remain. Below please find the schematic attached (Pierce Oscillator). 1 - When analysing the phase noise a "bump" appears by the end of the curve (both in strong and weak inversion). What is the reason for that (file attached...
Posted to
Custom IC Design
(Forum)
by
pcardoso73
on Sat, Apr 23 2011
Re: PSS, PNOISE and Transient Noise
Hello, Thanks for your answers. Relating to point 4, so if I choose either transient noise analysis or transient analysis without checking the transient noise analysis, the result of the Phase-Noise/Jitter calculations will be the same on the two cases, right ? Relating to your question in point 5, I...
Posted to
Custom IC Design
(Forum)
by
pcardoso73
on Mon, Apr 11 2011
PSS, PNOISE and Transient Noise
Hi all, I have several questions which i will describe by topics. All the circuit design is made in Candence using Spectre. 1 - As transient noise introduces noise in the transient simulation, I export the data to Matlab to perform the Jitter (RMS and Peak-to-Peak) calculations. How can I do this in...
Posted to
Custom IC Design
(Forum)
by
pcardoso73
on Tue, Apr 5 2011
PNOISE and Transient Noise
Hello all, I am doing a Phase Noise analysis, which I would like to convert to jitter. 1 - I am using a tran analysis+ PSS+ PNOISE and I get the Phase Noise out of this. How can I get the jitter ? 2 - The transient noise should be enable during the tran simulation , and use those data on PSS+PNOISE ...
Posted to
Custom IC Design
(Forum)
by
pcardoso73
on Thu, Feb 24 2011
Unable to plot phase noise
Hi, After running pnoise: jitter analysis, I wanted to plot the phase noise by choosing: Direct Plot Form => pnoise jitter => Phase Noise => dBc => Plot I got some error messages shown as follow: *Error* flip: can't handle flip(nil) *Error* flip: can't handle flip(nil) *Error* flip...
Posted to
Custom IC Design
(Forum)
by
sebastion
on Wed, Jul 21 2010
difference between the two phase noise functions in Direct Plot Form?
Hi, I am trying to simulate the phase noise of a 25GHz LC oscillator using pss (flexible balance) and pnoise analysis. In the Direct Plot Form, there are two different Phase Noise options: 1) Analysis: pnoise Function:Phase Noise 2) Analysis: pnoise jitter Function: Phase Noise The two above give different...
Posted to
RF Design
(Forum)
by
SonerYaldiz
on Sat, May 8 2010
how to capture 1/f noise in spectre
Hello I am designing a down-converter and need to capture 1/f noise corner. I need to find a way to capture the corner automatically after simulation (PSS and Pnoise) instead of using rulers to find it. Does anyone know how to grab it automatically? Thanks much in advance.
Posted to
RF Design
(Forum)
by
pureck
on Fri, Apr 9 2010
pss+pnoise analysis failure in Monte Carlo Simulation
Hi, I am trying to run a Monte Carlo simulation of a 25GHz LC-VCO (vco followed by an ac-coupled buffer) for phase noise (mmsim-7.11, pss (harmonic balance) and pnoise). When I try a single run (no variability), the simulation finishes successfully without any errors or warnings. When I try running a...
Posted to
RF Design
(Forum)
by
SonerYaldiz
on Wed, Jan 27 2010
Page 2 of 3 (24 items)
< Previous
1
2
3
Next >