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phase noise

  • Re: RE: Phase Noise vs frequency graph problem

    Hello Tawna, I am very thankful for your reply...Read a lot of posts by you and Andrew in various topics and a fan of your knowledge and work.. I got the correct graph yesterday when I changed errpreset to 'moderate' and putting tstab as 60n..but the values of phase noise was aroung -140dbc/hz...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
  • Re: Phase Noise vs frequency graph problem

    Thanks Frank for replying. Yes, I have seen that post-it explains the equation which spectre uses to find the pnoise...but it doesnt help me to get the right graph with negative values of pn. I am doing the pss-pnoise simulation using the following settings: PSS : Harmonic Balance beat freq - 37.93G...
    Posted to Custom IC Design (Forum) by rohan kr on Wed, Mar 28 2012
  • Phase Noise vs frequency graph problem

    Hello I am a newbie engineer starting my career in IC design and working on a high frequency oscillator (38 GHz). I am using Cadence IC6.1.5-64b.500 version and using spectre simulator for the schemtic design and simulations. I am having doubts about my 'pnoise' analysis. All the research papers...
    Posted to Custom IC Design (Forum) by rohan kr on Wed, Mar 28 2012
  • Transient noise

    Hi , What does the transient noise tab in the analyses window of spectre means and what were the values should be given for noise max. ,noise min and bins if my oscillator is working at 450MHzand running for 150ns. Thanks in advance. with regards, Jithin
    Posted to Custom IC Design (Forum) by Jithin on Wed, Mar 21 2012
  • Jitter from pnoise simulation

    I'm desinnig a Time to digital converter and I would like to simulate the jitter of a driven buffer having a rising time of 350 ps. In my schematic, the buffer is driven by vpulse (ideal CLK @ 2 MHz) and I would like to simulate his output jitter. My setting of pss simulation is as follow: Beat frequency...
    Posted to RF Design (Forum) by moez on Fri, Mar 9 2012
  • Cadence noise aware PLL design flow: have lock problem

    Hi All, It is a bit long story. I will try my best to explain it clear. Thanks for your patience to read it through and give me some feedback. Recently I tried to follow Cadence noise-aware PLL design flow (PLL Macro Model Wizard) to verify my design. (We got the PLL_workshop from Cadence already) I...
    Posted to RF Design (Forum) by lunren on Mon, Feb 6 2012
  • SpectreRF AppNotes and Tutorials....Still One of our Best Kept Secrets!

    Some of you may remember the blog written several years ago " Shhhhh...SpectreRF Tutorials and AppNotes - One of Our Best Kept Secrets ". Well, the more things change...the more things stay the same! The location of these tutorials and appNotes still seems to be one of our best kept secrets...
    Posted to RF Design (Weblog) by Tawna on Mon, Jan 16 2012
  • Q&A: TI Wireless Team Describes Advanced Phase-Noise Characterization for RF Oscillators Using SpectreRF

    In this interview, members of the Texas Instrument wireless group talk about the characterization effort initiated and completed last year between Cadence and IBM using TI RF designs as a pilot. The goal between the two teams was to optimize SpectreRF usage to successfully and efficiently simulate TI...
    Posted to RF Design (Weblog) by helenet on Wed, Jun 15 2011
  • Jitter in Strong and Weak Inversions

    Dear all, I have designed a crystal oscillator, but some doubts still remain. Below please find the schematic attached (Pierce Oscillator). 1 - When analysing the phase noise a "bump" appears by the end of the curve (both in strong and weak inversion). What is the reason for that (file attached...
    Posted to Custom IC Design (Forum) by pcardoso73 on Sat, Apr 23 2011
  • Re: PSS, PNOISE and Transient Noise

    Hello, Thanks for your answers. Relating to point 4, so if I choose either transient noise analysis or transient analysis without checking the transient noise analysis, the result of the Phase-Noise/Jitter calculations will be the same on the two cases, right ? Relating to your question in point 5, I...
    Posted to Custom IC Design (Forum) by pcardoso73 on Mon, Apr 11 2011
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