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  • pcell problem

    Hi, I have the following question. I updated our pdk (tsmc process) with some addons for rf devices and minor techlib tweaks. We have some special capacitors (crtmom). The pcell for this is working good, but if I open an old layout with pcells from before the chance I miss some layers (VIA2 and MET2...
    Posted to Custom IC Design (Forum) by Stefan Bormann on Mon, Mar 26 2012
  • Re: Is it possible to parameterize a Multi Bit wire with vector expressions?

    Hi Wes, I wrote some Schematic PCell code for this type of problem a while back, it may not be tested fully!! Here it is: /*Description: Sample PCell code for a schematic and a symbol PCell that is designed to be a "wrapper" around an existing cell, in this case the resistor from analogLib...
    Posted to Custom IC Design (Forum) by skillUser on Thu, Feb 2 2012
  • Re: layoutXL Gen from source doesn't give correct sizes.

    Well, turns out there is still an issue with the size of the Pcell. If I places the nsoi Pcell thru layoutXL gen from source I get the correct size transitors. If I instanciate the pcell from my layout cell I get very large transistors. This makes sence in the way I've changed the Pcell code to get...
    Posted to Custom IC Design (Forum) by MarkTown on Thu, Nov 17 2011
  • Virtuoso GDS Via Problem

    Hi! I'm having problems with vias, which are exportet to GDS files. I exportet the chip layout from Encounter to a GDS file: streamOut chip.gds.gz -mapFile ../setup/gds2.map -libName DesignLib -stripes 1 -units 1000 -mode ALL The GDS file is hierarchical and instanciates standard cells, io pad cells...
    Posted to Custom IC Design (Forum) by Johann Glaser on Tue, Aug 16 2011
  • symbol PCELL extraction issue.

    I have created a symbol, schematic and layout pcell. Everything seemed to be working correctly until I wanted to start LVS-ing the the pcell. I first ran into an issue where it required that my schematic be extracted since last edit. So I followed the instructions here: ___Schematic PCell: Schematic...
    Posted to Custom IC SKILL (Forum) by fishbulb15 on Fri, Jul 22 2011
  • Confused TechFile & Simulation

    Hello, I designed my own transistor layout by coding a SKILL pcell. The next thing should be a own spectre modle, but the only thing I can do right now is: -create a schematic view for my layout which would include a transistor out of my techfile Normaly I thought I would connect some kind of spectre...
    Posted to Custom IC Design (Forum) by eactor on Thu, May 12 2011
  • pcell conditional include default overrides any selection

    When I instantiate a pcell created with the pcell tool, the checkbox on the Create Instance form or Edit Instance Properties has no effect. The default state of the conditional include is shown. It used to work but with various edits has stopped doing so.
    Posted to Custom IC SKILL (Forum) by gkaatz on Thu, Apr 7 2011
  • How to know the name of the properties of the device without editing this property?

    For example: I want to know the name of length and width properties of the nmos without editing in these properties(its length and width) then using nmos->prop->?? that show me an array like the following ( "l" value "5u" valuetype "string" -----------) ( "w"...
    Posted to Custom IC SKILL (Forum) by dell1 on Wed, Apr 6 2011
  • User Presentation: Automatically Generated SKILL PCells Speed PDK Development

    Process design kit (PDK) developers have been using the SKILL language to code PCells (parameterized cells) for over two decades. SKILL is a flexible, extensible, Lisp-based language that can do just about anything a programmer wants to do. But is there an easier way to create PCells? Yes, according...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 1 2010
  • How to make AMS Netlister evaluate pcells

    Hi, I have built a schematic pcell which instantiates different cells according to a parameter. The AMS Netlister does not generate and include different instances per parameter-set in the netlist. If the generated pcell is placed several times with different parameters in a testbench, the normal spectre...
    Posted to Custom IC Design (Forum) by Marode on Wed, Apr 21 2010
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