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  • Defining a string parameter in a systemverilog model as a design variable

    Hi, I have a systemverilog module with a string parameter: parameter string filename = "default_name"; When I instantiate this module and edit its object properties, I see the filename property. Whatever I write into this field is passed as a string to the module. Is it possible to define a...
    Posted to Mixed-Signal Design (Forum) by Soner on Wed, Aug 21 2013
  • PSPice Ftable Parameters

    Hi there. I'm developing a circuit in PSpice including an Impedance-model, which is simulated within a real and a complex part. Also can be looked like a Resistor and a Capacitor that change values according to varying the frecuency. So, for example, I have: @35kHz: R=2000; C=2.27nF or also can be...
  • *Error* times: can't handle (3.0 * nil)

    I've been using the ADE-GXL optimization features on resistors and getting good results. I’ve now move to trying FETs and I’m getting some strange behavior. I'm using the optimizer to select the number of fingers for some FETs. If I set the finger parameters to be scale up to 5 (1...
    Posted to Custom IC Design (Forum) by BradW on Thu, Oct 25 2012
  • Model Parameters

    How to export the model file (*.scs) in Cadence ?
    Posted to Custom IC Design (Forum) by MasterPlane on Thu, Oct 18 2012
  • retain simulation trace

    Hi Forum, I'm using Pspice/Capture to model a solar panel. I'm using some reasonable complicated simulation traces to analyse the system. What is frustrating is each time I adjust a parameter or the simulation profile, I have to re-input the formula for each trace. Is there anyway to automatically...
    Posted to PCB Design (Forum) by SolarStudent on Sat, Jan 7 2012
  • Connect to PSPICE through command line

    Hi, I'm trying to run a pspice simualtion through command line. -What is the fastest way to do it? is it running "pspice.exe" or "psp_cmd.exe" or some other way? -what are the parameters for "psp_cmd.exe"? -the data in .out file have a very limited accuracy (say 1.65e...
    Posted to PCB Design (Forum) by Sohrab on Tue, Jan 3 2012
  • How to align a customed titleblock to design template in CIS schematic design?

    Hi, I defined a customed titleblock. But I don't know how to align the customed titleblock to the design template. How do the text in titleblock can automatically fill in the customed titleblock? Can the page number and page count be generated automatically as microsoft office word? If yes, how can...
    Posted to PCB Design (Forum) by Bejyuhan on Wed, Jun 29 2011
  • CDF parameters and AMS netlister

    Hi, I'm trying to do a mixed signal simulation with AMS. In my analog design i use CDF parameters to set transistor sizes. However, the components from the tech-lib i use calculate area values from the length and width values. Because of the Ppar("var") value of the sizes, the area calulation...
    Posted to Custom IC Design (Forum) by ArjanVanHeusde on Wed, Sep 8 2010
  • type parameter override

    Does NC support type parameter overrides? If not, why not? I'm attempting to use an interface wrapper with a typed parameter to pass interfaces to the drivers/monitors. But I get this error during compile: typedef virtual cllp_if #(.DW(16), .EW(6), .AW(14)) cllp_if_t; IfWrapper #(cllp_if_t) if_wrapper;...
    Posted to Functional Verification (Forum) by hab94 on Wed, Jul 21 2010
  • PSPICE tolerance a passed parameter

    I have 2 questions I have ran into while trying to run a monte carlo analysis: 1. How can I tolerance a parameter passed into a sub-circuit such that it will vary over a monte-carlo run? For instance, a 3 or 4 resistor values getting passed into a suckt as a parameter, but i would like it to vary one...
    Posted to PCB Design (Forum) by jake65892 on Tue, Jun 29 2010
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