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Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis
Cadence this week (May 20, 2013) announced the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure by a matter of weeks. One factor behind this...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 20 2013
EDA Workshop Debate Erupts Over Parallel Programming
The Electronic Design Processes (EDP) workshop may be a small, technical, IEEE-sponsored event, but that didn't stop a lively debate over the feasibility of parallel processing from erupting last week. The debate comes as EDA vendors, including Cadence, are working hard to port their software to...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Apr 12 2010
DAC Report: GPUs Or Multicore For EDA Applications?
The Wednesday keynote speech at the Design Automation Conference offered a strong argument for general-purpose graphical processing units (GPGPUs) as the best way to accelerate EDA and other compute-intensive applications. But whether GPGPUs will prove to be a better solution than more conventional multicore...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Fri, Jul 31 2009
Q&A Interview: Kurt Keutzer Charts Path To “Manycore” Parallelism
Kurt Keutzer, professor of electrical engineering and computer science at the University of California at Berkeley, believes that software applications including EDA tools can be re-architected to take advantage of “manycore” parallelism (32 cores or more). In this interview, he discusses...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 20 2009
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