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packaging
"PCB design"
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Turn GDSII Data into Intelligent Die Components with 16.6 Cadence APD/SiP Tools
As we all know, there are many file formats in which an IC package designer will receive a die from the IC designer. Ideally, it will be in a format such as die text or a co-design die abstract, as these files contain both logical and physical information in a single, comprehensive file. Reality is often...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Fri, May 3 2013
Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP
The level of ease and efficiency you experience in selecting the items needed for modifying in your substrate can mean the difference between a great design experience and an exercise in frustration and futility. With the 16.6 release, Cadence IC Packaging tools now offer an extended array of selection...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Thu, Apr 11 2013
Remove Die Stack Layers from NC Drill Outputs using Cadence 16.6 SiP and APD IC Packaging Tools
As we continue with our series on improvements to the manufacturing and documentation outputs in the Cadence 16.6 IC Packaging layout tools, our focus this week is on NC Drill outputs. For as long as NC Drill data has been a part of the IC Packaging tools, and the cross-sections in package designs have...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Fri, Mar 1 2013
Ease Your IC Packaging Documentation and Manufacturing Exports for Stacked Dies in 16.6 SiP
Following our last posting concerning intelligent documentation text, this week we look at the a new ability in 16.6 for managing the die outlines in a manner which allows simplified generation of documentation and manufacturing outputs. In a complex IC package substrate, all die components may not be...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Wed, Feb 6 2013
Make Your IC Packaging Documentation Labels Smarter with 16.6 SiP and APD
Documentation is key when completing any IC package substrate design. Without it, any number of problems can arise - from incorrect bond mapping between die pads and bond fingers to die being stacked in the wrong order. Ensuring that your documentation text labels are not only present, but are up to...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Thu, Jan 17 2013
CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification
A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 9 2013
Be Among the First IC Packagers to Experience the New GDS-II Stream Interface in 16.6
For most IC package designers, the GDSII format is a part of daily life. You may receive stream data from your IC designers or partners which you must convert into die components for placement on a package substrate, or perhaps you export stream data as part of your manufacturing and documentation process...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Thu, Dec 20 2012
Martin Lund Keynote: Time to Rethink Semiconductor IP “Reuse”
People have been talking about semiconductor IP "reuse" for many years, but is IP really reusable as is? It's increasingly unlikely, according to Martin Lund (right), senior vice president of the SoC Realization Group at Cadence. In a recent keynote speech, Lund said that continuous changes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 19 2012
Open Cavity Design Tools for IC Packaging Now Available in 16.6
In version 16.5 of the Cadence IC package layout tools, we introduced embedded discrete component support. With the 16.6 release, that support has been extended even further. You are now able to define both manual and automatically-managed open cavities in which you can place your dies and die stacks...
Posted to
IC Packaging and SiP
(Weblog)
by
Jeff Gallagher
on Tue, Nov 27 2012
What's Good About APD’s Shape Shorting? You’ll Need the 16.6 Release to See!
In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with...
Posted to
PCB Design
(Weblog)
by
Jerry GenPart
on Tue, Nov 13 2012
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