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package

  • Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

    Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 25 2012
  • Component Browser: Footprint is not defined for a part.

    Hi, After creating part/symbol in Part Developer using PCB Librarian, I tried to test the part in DE HDL through PCB Librarian. When I placed the part, Component Browser shows an error, Footprint is not defined for a part. What might be the cause of this error? But when I tried to export the schematic...
    Posted to PCB Design (Forum) by maberu on Thu, Jul 19 2012
  • Re: Can't place parts in Orcad PCB... Solved! :-)

    Thanks to NordCad for the solution! You/I should be seeing check boxes to the left of refdes in the manual placement dialogue box! I didn't. It seems this is a issue with Windows 7. The text of the dialogue boxes is a bitmapped font - and the default Windows 7 fonts scales the text "over"...
    Posted to PCB Design (Forum) by N i z e on Fri, Nov 4 2011
  • Package to package clearance

    Hello everybody! Another newbie here! My issue goes as follows: I am building my component symbols libraries for my project, and am working with the design guidelines from the PCB manufacturer. There, they require what they call a " Placement Keepout Area to Neighboring Component Placement Keepout...
    Posted to PCB Design (Forum) by RiskCord on Thu, Aug 25 2011
  • EDA360 Beyond the Chip – Package, Board, and Product Creation

    The EDA360 vision , articulated by Cadence one year ago this week, calls for an expanded view of EDA that supports complete hardware/software systems ready for applications deployment. Most of the discussion during the first year focused on silicon and embedded software. A Cadence Allegro 16.5 announcement...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 25 2011
  • Package creation - Allegro

    Prepare for a very basic question: Does anyone know of a good tutorial that tells me how to create a new footprint? I (think I) understand how to modify the padstack, but I'm not sure where or how to enter a footprint for a part that's not in the default library. For example, I would like to...
    Posted to PCB Design (Forum) by ChrisL2 on Tue, Jan 18 2011
  • Favorite Features of an IC Package Designer: Wirebonding

    This is the fourth in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. While wirebond packages are nothing new, the challenges associated with package designs using wirebonds have continued to grow. Stacking die...
    Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Mon, Nov 8 2010
  • Favorite Features Of An IC Package Designer: Assembly Rule Checks

    This is the third in a series of discussions we would like to open up regarding "favorite features" in an IC Packaging implementation design tool. As the industry continues to include larger numbers of larger die in a smaller IC package, the question of "Can this be manufactured?"...
    Posted to IC Packaging and SiP (Weblog) by TeamAllegro on Wed, Jul 28 2010
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