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  • Taming the Challenges of IC Design

    AUSTIN, Texas--You want the bad news first or the good news about IC design challenges? Let's start with the bad news: As IC design moves into 20nm and 16nm nodes, the challenges facing not only designers but EDA vendors are extraordinary if the industry is to maintain momentum and design productivity...
    Posted to The Fuller View (Weblog) by Brian Fuller on Wed, Jul 24 2013
  • DAC 2013 Panel: What’s Needed to “Fix” Timing Signoff?

    Has timing signoff innovation become an oxymoron? What happened and how do we fix it? That was the provocative title of a Cadence-sponsored lunch panel at the Design Automation Conference ( DAC 2013 ) June 3. Panelists from ARM, Altera, GLOBALFOUNDRIES, and Cadence talked about the challenges of timing...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 4 2013
  • Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

    Anirudh Devgan is corporate vice president of R&D for Silicon Signoff and Verification, which is part of the Silicon Realization Group at Cadence. Last week (May 20, 2013) Cadence announced the first new product in this space, the Tempus Timing Signoff Solution . Tempus provides up to an order of...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 28 2013
  • ARM and Cadence Improve Cortex-A Power and Performance with Optimized Flow

    For several years, ARM has offered processor optimization utilities (called POPs) that help users of ARM Cortex-A series processors optimize power, performance and area for a given process. This week (Aug. 9) ARM and Cadence took things one step further by announcing a POP that includes scripts that...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 9 2012
  • The Science of Synthesis

    I am passionate about synthesis. Almost 20 years ago I began using Synopsys "Logic Compiler" to do combinational synthesis and optimization from Verilog RTL. At that time it did not support sequential constructs so Flip-Flops had to be manually instantiated in the netlist. Synthesis has matured...
    Posted to Logic Design (Weblog) by Jason Ware on Mon, Dec 8 2008
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